Domain-Specific High Level Synthesis of Floating … – TUprints

In the early seventies semiconductor companies developed a mask-pro- … In addition to low latency data transfers, this design allows cache co- herency between … 3 DSP. LUT (BRAM). X. Y. Mul1. 3 DSP. Mul2. 3 DSP. ̷ 53. ̷ 8. ̷ 42. Mul3.