VC709 Evaluation Board for the Virtex-7 FPGA User … – Xilinx

IIC_SDA_SCL, pin AT35), which is routed through a TI Semiconductor … User applications that communicate with devices on one of the downstream … J5 pin 10 net PMBUS_DATA is level-shifted to 1.8V by Q6 and is connected to U1 bank 15.